1. Field of the Invention
The present invention relates to a power semiconductor device and, more particularly, to a structure of IGBT (Insulated Gate Bipolar Transistor).
2. Description of the Related Art
An IGBT is a transistor having a sectional structure represented by FIG. 1 and has a composite structure having a MOSFET (metal oxide semiconductor field effect transistor) structure section at an upper portion and a bipolar transistor structure section at a lower portion. The structure and operation of the transistor are disclosed in the specification and drawings of Published Examined Japanese Patent Application No. 57-120369. FIG. 1 especially shows an n-channel IGBT. In the IGBT shown in FIG. 1, an n.sup.+ -type buffer region 102 and an n.sup.- -type drain region 103 are sequentially formed on one major surface of a p-type substrate (anode) 101, a p-type base region 104 is formed in the n.sup.- -type drain region 103 by an impurity diffusion method, and an n.sup.+ -type source region 105 is formed in the p-type base region 104 by an impurity diffusion method. A thin oxide film 106 (dielectric layer) is formed on the semiconductor body, and a polysilicon gate electrode 107 is formed on the oxide film 106. A metal source electrode 108 is formed on the semiconductor body such that the p-type base region 104 and the n.sup.+ -type source region 105 are short-circuited. A metal gate electrode 109 and a metal anode electrode 110 are formed on the polysilicon gate electrode 107 and the other major surface of the p.sup.+ -type substrate (anode) 101, respectively.
The source electrode 108 is grounded, and a positive voltage is applied to the anode electrode 110. In this state, when the gate electrode 109 is kept at a negative potential, the semiconductor device is in an OFF state. When a positive voltage is applied to the gate electrode 109, an inverted channel 111 is formed on the surface region of the p-type base region 104, as in a conventional MOSFET. In addition, some of electrons flow in to a surface portion 112 of the n.sup.- -type drain region 103 from the n.sup.+ -type source region 105 through the channel 111 to form an electron storing layer. Other electrons are moved in the n.sup.- -type drain region 103 toward the anode electrode 110 side by a voltage applied between the source and anode, and a junction between the p.sup.+ -type anode region (substrate) 101 and the n.sup.+ -type buffer region 102 is forward-biased. Thus, holes are injected from the p.sup.+ -type anode region 101 into the n.sup.- -type drain region 103 through the n.sup.+ -type buffer region 102, and the conductivity in the n.sup.- -type drain region 103 is modulated to cause the semiconductor device to be in an ON state. In this state, when the gate electrode 109 is returned to zero or a negative potential, the channel 111 is closed, and the semiconductor device is returned to an OFF state.
The most serious drawback of the above structure is that a parasitic thyristor is formed. That is, the parasitic thyristor is constituted by a parasitic npn transistor constituted by the n.sup.+ -type source 105, the p-type base 104, and the n.sup.- -type drain 103, and a parasitic pnp transistor constituted by the p.sup.+ -type anode 101, the n.sup.- -type drain 103, and the p-type base 104. When this parasitic thyristor is turned on, although the channel 111 is closed, an electron flow from the n.sup.+ -type source 105 to the n.sup.- -type drain 103 is maintained by the parasitic npn transistor. For this reason, the device cannot be returned to an OFF state to cause the device to be broken down.
Therefore, in the IGBT device, it is technically important to suppress the turn-ON of the parasitic thyristor, to increase a maximum controllable current as a transistor, and to widen a safe operation area.
These points are disclosed in Published Unexamined Japanese Patent Application No. 57-120369, and a conventional method of controlling the turn-ON of the parasitic thyristor teaches the following:
(1) any means is provided to make it difficult to turn on the parasitic npn transistor; and
(2) gains .alpha..sub.npn and .alpha..sub.pnp of the parasitic npn and pnp transistors are decreased to make it difficult to establish .alpha..sub.npn +.alpha..sub.pnp .gtoreq.1.
As the second drawback of the IGBT, it is known that a turn-OFF time is long. This is because minority carriers injected from the p.sup.+ -type anode 101 to the n.sup.- -type drain 103 are stored in the n.sup.- -type drain 103 as excess carriers. Although the channel 111 is closed to stop an electron flow, the device is not returned to an OFF state until the stored minority carriers are swept. As a technique for solving the above problem, it is known that the life time of the carriers is shortened, thereby increasing a recombination speed of the stored carriers, and that the turn-OFF time is shortened. In order to practically shorten the life time of the carriers, the following methods are used:
(1) an impurity having a deep level such as gold or platinum is diffused in the substrate; and
(2) high-energy particles such as electrons or neutrons are radiated on the substrate to form a recombination center in a silicon bulk.
By forming this recombination center, the turn-OFF time is shortened, and the gains .alpha..sub.npn and .alpha..sub.pnp are decreased. Therefore, the turn-ON of the parasitic thyristor is suppressed in comparison with a case where the recombination center is not formed.
When gold is diffused in the substrate, it is known that the gold functions as an accepter, and that the resistivity of the n.sup.- -type drain region is increased by a concentration compensation effect. When the life time of the IGBT is practically controlled by a gold diffusion method to obtain a turn-OFF time of 1 .mu.s or less, the concentration compensation effect occurs throughout the entire range of the n.sup.- -type drain region 103, and the resistivity is increased throughout the entire range. In order to decrease the resistivity of the region 112, it is proposed that an n-type impurity concentration of the region 112 is increased (PCIM'88 proceedings pp. 134).
The concentration compensation effect caused by a gold diffusion method is conspicuous near the silicon surface. For this reason, a satisfactory electron storing layer is not formed in the region 112 immediately below the oxide film (dielectric layer), and the current conductivity is decreased.
In order to form a satisfactory electron storing layer, the structure shown in FIG. 2 is proposed in the above Published Unexamined Japanese Patent Application No. 57-120369. In this structure, an n.sup.+ -type region 201 having an impurity concentration of 10.sup.18 to 10.sup.20 atm/cc as an electron storing layer is formed.
When the life time is controlled by diffusing platinum, though it is a heavy metal, the above concentration compensation effect is extremely small. In addition, when the life time is controlled by irradiation of an electron beam, a neutron beam, or the like, the above effect is also extremely small. Therefore, in either case, the decrease in current conductivity due to degradation of an electron storing effect hardly occurs.
Conventionally, an IGBT having a turn-OFF fall time of about 0.3 .mu.s is obtained by life time control using a heavy metal diffusion method with gold, platinum, or the like. However, in the heavy metal diffusion method, diffusion controllability is poor. In practical manufacture, the device is manufactured such that the turn-OFF fall time tf has a width of 0.3 .mu.s to 0.8 .mu.s, and variations in turn-OFF fall time are large. In order to obtain IGBT characteristics of the turn-OFF fall time tf of 0.3 .mu.s or less, a large amount of heavy metal must be diffused. However, when the heavy metal diffusion is performed on this order, not only is the leak current increased in the bulk silicon, but the surface leak current due to segregation in an interface between a silicon surface and a thermal oxide film is also increased. Therefore, the device cannot be used in practice.
According to the development of a life time control technique by an electron beam irradiation or a neutron beam irradiation, the variation in turn-OFF fall time tf is within 0.1 .mu.s, and the turn-OFF fall time tf is 0.3 .mu.s or slightly less than 0.3 .mu.s. According to the further development of the life time control technique by this type of irradiation, the turn-OFF fall time of 0.15 .mu.s or slightly less than 0.15 .mu.s can be obtained. As a result, an IGBT serves as a high-speed turn-OFF device similar to a conventional MOSFET.
According to the development of the life time control method, since a short life-time can be achieved, the gain .alpha..sub.pnp can be decreased. According to this, a maximum controllable current can be increased.
However, when the life time control is performed such that the turn-OFF fall time tf is 0.3 .mu.s or less, the maximum controllable current is saturated. When the life time control is performed such that the turn-OFF fall time tf is 0.2 .mu.s or less, the maximum controllable current is decreased. This operation is shown in FIG. 3. Reasons for this can be considered as follows.
That is, in a region in which a life time is relatively long, since the gains .alpha..sub.npn and .alpha..sub.pnp are large, a total gain .alpha..sub.npn +.alpha..sub.pnp easily exceeds "1", thereby limiting the maximum controllable current. In order to increase the maximum controllable current, therefore, the life time of carriers must be shortened to decrease the total gain .alpha..sub.pnp +.alpha..sub.npn. However, when the carrier life time is significantly shortened, the parasitic npn transistor is turned on with a smaller current, and the effect of the degradation of the gain .alpha..sub.pnp cannot be contributed.
In other words, in a region where the carrier life time is sufficiently short, i.e., the life time is 0.5 .mu.s and the turn-OFF fall time tf is about 1 .mu.s or less, it can be considered that the maximum controllable current of the device is determined by a current density obtained when the parasitic npn transistor is turned on.
In the parasitic npn transistor, the n.sup.+ -type source 105 serving as an emitter and the p-type base 104 serving as a base are shunt-short circuited by the source electrode 108. However, as shown in FIG. 4, holes "h" injected from the p.sup.+ -type anode region 101 (in FIG. 1) flow as a hole current into p-type base region 104 while attracted by electrons "e" and are collected to the source electrode 108 through the portion below the n.sup.+ -type source region 105. By a part Ih' of this hole current and a resistance R of the p-type base region 104 below the n.sup.+ -type source region 105, a voltage drop of Ih'.times.R occurs. As a result, a p-n junction between the n.sup.+ -type source region 105 and the p-type base region 104 is forward-biased. When this forward bias exceeds a built-in voltage of the p-n junction, the electrons "e" are injected from the n.sup.+ -type source region 105 to the p-type base region 104 to turn on the parasitic npn transistor.
An influence of shortening the carrier life time on a turn-ON mechanism of the parasitic npn transistor will be described below.
FIGS. 5 and 6 schematically show a flow of the hole current Ih' on the basis of analysis result obtained by calculation. FIG. 5 shows a case wherein a life time is relatively long (to 5.times.10.sup.-7 s), and FIG. 6 shows a case wherein a life time is short (to 5.times.10.sup.-8 s).
In a conventional IGBT structure, when a carrier life time is long, electrons "e" which flow in the n.sup.- -type drain region 103 through the channel 111 are diffused below the p-type base region 104. For this reason, the holes h injected from the p.sup.+ -type anode region 101 almost uniformly flow in the n.sup.- -type drain region 103 and flow in the p-type base region 104 therefrom.
However, the distribution of the electrons "e" is localized near the electron storing layer 112 by shortening of the carrier life time, and, as shown in FIG. 6, the holes h are attracted in a direction of the electron storing layer 112. As a result, the holes h flow in the p-type base region 104 from only near the electron storing layer 112, i.e., only the side surface of the p-type base region 104 and are localized. Therefore, when the carrier life time is sufficiently short, the hole current Ih' concerning the voltage drop is increased. In other words, in FIG. 5, since R1 to R3 are relatively small, the voltage drop is calculated by the following equation: EQU R4.times.Ih4'+R5.times.Ih5'.apprxeq.R5.times.(2/5)Ih
In FIG. 6, the voltage drop is increased to the value calculated by the following equation: EQU R5.times.Ih'=R5.times.Ih
Therefore, a forward bias between the emitter (N.sup.+ -type base region 105) of the parasitic npn transistor and the base (p-type base region 104) is deepened, and the parasitic npn transistor is easily turned on.